The present invention relates to insulated gate field effect transistors (IGFETs) such as metal oxide semiconductor field effect transistors (MOSFETs). More particularly, the invention relates to vertical MOSFETs used in power applications, such as vertical, double diffused MOSFETs, commonly referred to in the industry by such terms as VDMOS, DMOS, HMOS, TMOS and HEXFET (HEXFET being a TM of International Rectifier, El Segundo, CA).
In a conventional vertical MOSFET, source and drain regions are provided on opposite surfaces of a semiconductor pellet. A body region is disposed between the source and drain regions, and during MOSFET operation, current flows between the source and drain regions through a channel within the body region. The channel is commonly provided on the same semiconductor surface as the source region, although in certain designs, sometimes referred to as VMOS, the channel is disposed on the surface of a groove in the semiconductor surface. The channel is conventionally described in terms of its length, i.e. the spacing between the source and drain regions at the semiconductor surface, and its width, i.e., the dimension perpendicular to the length. Channel width, which might conveniently be measured in units of centimeters, is typically far greater than channel length, which is frequently measured in units of microns.
Current flow through the channel is controlled by the voltage applied to an overlying gate. It is usually desirable to have a small channel length for ease of electrical switching, and to have a large channel width for increased current carrying ability and reduced on resistance, R.sub.ON. Conventional channel configurations include a single meandering line, a plurality of stripes, and a plurality of cells of a particular geometric shape arranged in a matrix.
In a vertical MOSFET power device, the semiconductor surface from which the source region and channel extend can be considered to comprise two major areas; (1) an active, gate-controlled portion, and (2) an adjacent inactive, perimeter portion. As the nomenclature implies, the active, gate-controlled portion is surrounded by the inactive portion; the inactive portion extending to the edge of the semiconductor pellet. The active, gate-controlled portion encompasses the area covered by the channel(s). The inactive, perimeter portion typically incorporates a voltage-supporting means such as a field plate, a mesa edge, a passivation coating, or some combination of these structures. An example of a field plate which might be used at the inactive perimeter portion can be found in SEMICONDUCTOR POWER DEVICES by S. K. Ghandi, John Wiley & Sons, 1977, pp. 66-70.
Within the general framework of conventional vertical MOSFET structures, we have discovered a modification which serves to increase the device current carrying capability and to decrease its R.sub.ON. Furthermore, our invention can be implemented into a conventional device fabrication process with relative ease.